DRV 2008 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

As silicon based CMOS technologies are fast approaching their ultimate limits, reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk. In particular, variability of process, voltage and temperature represent a significant threat not only for parametric yield but also for reliability, since they induce timing faults that are extremely difficult to detect during manufacturing testing. It results on increasing ratio of circuits passing fabrication test that are susceptible to manifest failures in the field.

These problems are creating barriers to further technology scaling and are forcing the introduction of new process, design and test solutions aimed at maintaining acceptable levels of reliability.

As elimination of these issues is becoming increasingly difficult, various design techniques are emerging to circumvent them. These techniques may incur area, power, yield or performance penalties. Thus, to enable their adoption by the industry there is need for novel solutions to minimize penalties and provide automation tools.

The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost.
Representative topics include, but are not limited to:

Reliability issues in advanced CMOS
Variability-aware design
Radiation effects in advanced CMOS
Design for reliability in advanced CMOS
Fault tolerant architectures
Variability mitigation
Self-calibrating architectures
On-line monitoring of circuit parameters
Design automation for self-calibrating and fault tolerant architectures
Variability insensitive architectures
Reliability assessment tools

The Venue

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The Workshop will be held at the Santa Convention Center, 5001 Great America Parkway (corner of Tasman Drive), Santa Clara, California 95054 and the adjacent Hyatt Regency Santa Clara Hotel. Santa Clara is the center of Silicon Valley, an hour south of San Fancisco. The convention center is adjacent to the Santa Clara Golf and Tennis Club. Also nearby is the interactive Intel Museum. There are many restaurants at the Mercado Santa Clara entertainment and food complex, Rivermark Plaza and Santana Row. For more information about Santa Clara, visit http://santaclara.org.

Workshop Registration

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Complete registration for the conference online, or by filling out and sending in this registration form.

Advance Program

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Thursday -- Friday

October 30, 2008 (Thursday)

2:00 PM - 7:00 PM REGISTRATION

4:00 PM - 5:30 AM	OPENING SESSION
4:00 PM - 4:30 PM	Opening Address
4:30 PM - 5:30 PM	Keynote: Resilient Design - an Affordable Solution for Variability and Reliability Shekhar Y. Borkar, Intel

5:30 PM - 6:30 PM	Session 1 - QUALITY AND YIELD Chair: TBD
	Variability beyond the buzz-word: Challenges of maintaining high quality designs in an increasingly non-linear design space. Stefan Eichenberger, NXP
	Data learning based tools and methodologies for timing yield improvement Li-C. Wang, UCSB

7:00 PM - 9:00 PM WELCOME RECEPTION

October 31, 2008 (Friday)

7:30 AM - 9:00 AM REGISTRATION

8:00 AM - 10:00 AM	Session 2 - RELIABILITY ASSESSMENT TECHNIQUES Chair: Norbert Seifert, Intel
	Reliability Simulation of Analog ICs under Time-Varying Stress in Nanoscale CMOS Elie Maricau, Georges Gielen, Katholieke U. Leuven
	Computing Bounds for Fault Tolerance using Formal Techniques A. Sulflow, G. Fey, S. Frehse, U. Kuhne, R. Drechsler, U. Bremen
	Improving Defect Detection in the Presence of Process Variations J.M. Howard, S.M. Reddy, I. Pomeranz, U. Iowa
	ATPG for Increased Test Quality and In-field Reliability M. Tehranipoor, U. Connecticut

10:00 AM - 10:30 AM COFFEE BREAK

0:00 AM - 0:00 AM	Panel - EARLY-LIFE FAILURES Organizer: Subhasish Mitra, Stanford U. Moderator: Rob Aitken, ARM
	Participants: Vikas Chandra, ARM Amr Haggag, Freescale Amit Majumdar, AMD/ATI Arman Vassighi, Intel TBD

12:00 PM - 1:00 PM LUNCH

1:00 PM - 2:30 PM	Session 3 - DESIGN FOR RELIABILITY AND VARIABILITY Chair: Shaleen Bhabu, Cadence
	Modeling and Simulation Tools for Resilient Nanoelectronic Design Yu Cao, Arizona State U.
	System-level Design of a Self-healing Reconfigurable Output Driver P. De Wit, G. Gielen, Katholieke U. Leuven
	Variation Aware Low Power Buffered Interconnect Design A. Narasimhan, Ramalingam Sridhar, SUNY Buffalo

2:30 PM - 4:00 PM	Session 4 - HIGH LEVEL APPROACHES Chair: Nacer-Eddine Zergainoh, TIMA
	Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms Qiang Xu, Chinese University of Hong Kong
	On the Reliability Modeling of Embedded Hardware-Software Systems M. A. Kochte, R. Baranowski, H.-J. Wunderlich, U. Stuttgart
	Balancing H/W and S/W to achieve cost effective product reliability Shawn Morrissey, CISCO

More Information

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Michael Nicolaidis, TIMA Laboratory	Yervant Zorian, Virage Logic
Tel: +33476575060 Fax: +33 4 76 57 49 81 Email: michael.nicolaidis@imag.fr	Tel: +1 (510) 360-8035 Fax: +1 (510) 360-8078 yervant.zorian@viragelogic.com

Committees

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Organizing Committee

General Chairs
Michael Nicolaidis, TIMA
Yervant Zorian, Virage Logic

Vice General Chair
Rajesh Galivanche, Intel

Program Chairs
Lorena Anghel, TIMA
Kaushik Roy, Purdue University

Vice Program Chair
Shi-Jie Wen, Cisco

Publicity Chair
Yiorgos Makris , Yale University

Panel
Subhasish Mitra, Stanford University

Program Committee

Jacob Abraham, Univ. of Texas
Bashir Al-Hashimi, U. Southampton
Shaleen Bhabu, Cadence
Nematolahh Bidokhti, Cisco
Vikas Chandra, ARM
Abhijit Chatterjee, Georgia Tech
Praveen Elakkumanan, IBM
Saibal Mukhopadhyay, Georgia Tech
Rubin Parekhji, Texas Instruments
Sachin Sapatnekar, Univ of Minesota
Norbert Seifert, Intel
Charles Slayman, Sun
Ming Zhang, Intel

For more information, visit us on the web at: http://obaldia.imag.fr/drvw/

The 1st IEEE Workshop on Design for Reliability and Variability (DRV2008 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.